Introduction

 

DC7 is a very fast 490 bit Data Comparator implemented with high speed 1.2 micron CMOS process.  The Data Comparator consists of seven long 70-bit Shift Registers with independent data input, data output, and data compare output.  The Shift Registers can work either in series or in parallel.  A global compare output provide the OR'ed result of all the data compare outputs.  The Shift Registers can be clocked at a 50 MHz rate for high speed detection of complicated patterns in digital data stream.

 

DC7 chip is designed for expandibility.  Many of them can be connected to form arrays of two or more dimensions to handle complicated digital patterns in large data streams.

 

Main Features

 

*          7 simultaneous 70-bit comparisons

*          Each bit has a shift register, a pattern

            register and a mask register

*          1470 bits of memory

*          Data chaining for longer comparisons

*          Parallel expansion for wider data

            words

*          50 MHz clock rate

*          Global compare output to facilitate

            interrupts to host computer

*          Small silicon die

*          Popular 40 pin DIP package

 

Signals and Pins

 

D0-6    Data input

Q0-6    Data output - delayed 70 cycles

C0-6    Data compare output, low if data          match pattern

C         Low if some match, (AND of C0-6)

Kd       Data clock.  Latch data on rising          edge, output data on falling edge

Kp       Latch pattern from data when high

Km      Latch mask from data when high

Ti         Test input

T          Test output

Figure 1.  Pinout of DC7 Chip

 

 

Timing

 

                                    min      max     (ns)

 

Setup: D - Kd 10

Hold:               Kd - D 10

Delay: Kd - C            20

Clock high:      Kd      10

Clock period:   Kd      20

Data latch:        Kp      10

Mask latch:       Km     10

Rise/fall:           all       10

 

Power-Up

 

All bits in the shift registers, the pattern registers and the mask registers are reset to 0.  Hence all the compare outputs are also reset to 0.  Shifting an 1 bit into any shift register will cause the corresponding compare output to go high, indicating that the contents of the shift register are not the same as those in the pattern register.

 

 

Operation

 

The DC7 contains seven 70-bit long Shift Register latched at the rising edge of Kd.  After the Shift Registers are filled, the data bits can be stored into a 490-bit Pattern Register by a rising pulse on Kp.  Another set of bits can be stored into a 490-bit Mask Register by a rising pulse on Km.  Thereafter, data in the Shift Registes are compared with the Pattern Registers.  7 output bits are available, one for each Shift Register, after the falling edge of Kd.  Match output (0) requires all 70 data and pattern bits be the same unless the mask bit says ignore (1).

 

A data bit appears at the Q output delayed by 70 cycles.  For a longer comparison, Q output can be fed into another Shift Register on the same chip or on another DC7.

 

The basic structure of this Data Comparator is shown in Figure 2.  It contains seven large Shift Registers, each is associated with a Pattern Register, and a Mask Register.  All three registers have the same length of 70 bits.  On every clock cycle of Kd, a new bit is shifted into a Shift Register at Dn and the oldest bit is shifted out of Qn.  The bit pattern in the Shift Register is compared with that in the Pattern Register.  The resulting bits, after masked by the bit patterns in the Mask Register are AND'ed together to produce a single Compare bit Cn.  The Mask Register allows patterns to be selectively ignored, thus greatly increase the flexibility of pattern matching.

 

Binary data are fed into the Shift Registers serially.  Since the other end of a Shift Register is brought to an output pin, many Shift Registers can be connected in series to increase the depth of the bit patterns to be searched.  If the chip is used to search text data, which are represented by 7-bit words, the seven Shift Registers can be clocked in parallel.  For data patterns wider than 7 bits, several DC7 chips can be connected in parallel to increased the width of data pattern.  Many DC7 chips can be connected in series to increase the depths of data patterns.

 

The Pattern Register and the Mask Register are loaded from the Shift Register with the PatternLoad Kp and MaskLoad Km inputs.  On the rising edge of the load input, data in the Shift Registers are loaded in to the respective Pattern or Mask Registers.  To initialize a chip to search for a particular bit pattern, the target pattern is first loaded serially into the Shift Register.  The PatternLoad pin is raised and  then brought to ground, which causes the data in the Shift Register to be loaded into the Pattern Register.  Similarly the Mask Register must be loaded with a mask pattern, which determines which bits are to be ignored in the comparison.  A high bit in the Mask Register marks the corresponding bit in the Pattern Register as a don't-care bit.

 

The logic circuitry of this Data Comparator is shown in Figure 3.  Each bit is handle by a shift register, two latches, and two gates.  This group of logic forms a cell which is replicated 7x70 times to form a complete chip.  Since the data is processed serially, the pinout of the chip is very simple and a 40 pin DIP package is used to house the chip.

 

Although the design of this chip is optimized for data comparing, its application is not limited to data comparing alone.  Any application in which pattern matching is needed can use this chip.  Some obvious applications are: data decryption, sync separation in disk drive controller,  spread spectrun detection, file maintenance, image processing and understanding, etc.

 

Since the logic in each cell is very simple and not many gates are involved, this chip runs at very high speed.  The current production chip runs at 50 MHz clock rate.

 

 

 

Figure 2.  Schematics of DC7

 

 

Applications

 

DC7 as a fast and flexible data comparator is well suited for applications in searching digital patterns and signatures in data bases and in real time digital singal streams.  Some examples of potentail applications are:

 

*    Text string search in large text  database

*    DNA pattern search in gene banks

*    Spread spectrum communication

*    Pattern recognition in digital signal   processing

*    Feature identification in image processing

*    Digital data decryption

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

More Information

 

For pricing, availablity, technical assistance, and additional information, please contact:

 

Offete Enterprises

1306 South B Street

San Mateo, CA 94402

(415) 574-8250

 

Figure 3.  Logic of DC7